[MZ series] Overclocking Z80

psmart
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Re: [MZ series] Overclocking Z80

Post by psmart » Mon Aug 03, 2020 10:55 pm

So which case is the two-clock source doing in the schematic?
Just re-reading your information, the clock circuit is operating asynchronously of the Z80, the two clocks can be out of phase and frequency. When a switch occurs the MARK is elongated so in turn whatever the Z80 was doing at the time of switch will be extended until the selected clock starts driving and then the Z80 continues on at the new clock frequency.

If your overclocking the mainboard then you would need to look not only at the instruction fetch cycle (is the wait state generator asserting the wait state at the correct time with the new frequency), you would also need to look at the Memory R/W and IO R/W cycles as the Chip selects from the gate array may be skewed.

Only way to find out is to try it, dont add a frequency switch, just manually increase the standard run frequency and observe the effects, good basis then as to what needs changing/delaying.

hlide
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Joined: Thu Jan 25, 2018 9:31 pm

Re: [MZ series] Overclocking Z80

Post by hlide » Tue Aug 04, 2020 4:39 pm

Ok, so your two-clock circuit is extending the MARK if necessary. That is what I wanted to do more or less few years ago with the idea to add a fast SRAM to replace the DRAM. Full speed when running in SRAM, original speed otherwise. But there was still the issue with memory or I/O port access to motherboard components which also need to done at original speed because you cannot execute them from SRAM.

What follows only concerns a genuine MZ-700:

As a fact, LSI and CPU should be okay up to 5xPHI. Why? The PAL main frequency which drives the LSI is around 17.73MHz. That ASIC is deriving the main frequency into several ones: Z80 clock (PHI) being that main frequency divided by 5. Since the Z80 is a CMOS Z84C0020PEC, it shouldn't be an issue to run at 5xPHI, that is, 17.73MHz. Or even at 4xPHI, that is, 14.18MHz which is close to the NTSC main clock (and so the PCB could work on both versions with no changes).

VHDL parts are from GDG1500 (LSI implementation for MZ-1500).

The only I/O ports are:

Code: Select all

PRC <= '0' when (nIORQ = '0') and (A(7 downto 1) = "1111111") else '1';
process(nRESET,A,nWR,nIORQ,Z80CLK)
begin
  if (nRESET = '0') then 
    INH1 <= '1';
    INH2 <= '1';
    INH3 <= '1';
  elsif (rising_edge(Z80CLK)) then
    if (nIORQ = '0') and (nWR = '0') and (A(7 downto 3) = "11100") then
      if (A(2 downto 0) = 0) then
        INH1 <= '0';
      elsif (A(2 downto 0) = 1) then
        INH2 <= '0';
      elsif (A(2 downto 0) = 2) then
        INH1 <= '1';
      elsif (A(2 downto 0) = 3) then
        INH2 <= '1';
      elsif (A(2 downto 0) = 4) then
        INH1 <= '1';
        INH2 <= '1';
        INH3 <= '1';
      elsif (A(2 downto 0) = 5) then
        INH3 <= '0';
      elsif (A(2 downto 0) = 6) then
        INH3 <= '1';
      end if;
    end if;
  end if;
end process;
If the original LSI is doing that way, I'm pretty sure it can deal with a Z80CLK up to 5xPHI.
But considering the fact those I/O ports are not critical in speed it is okay to execute them in the original speed.

The main components on the motherboard which may be sensitive to timing are:
- IC 8E: 8255
- IC AG: 8253C
- IC (7-A)(H-J): 4164C-3
- IC 5H: 2732
- IC (8,A)A: 2016P-1

So they are critical enough to force executing the T-state(s) triggering them in the original speed.

Now most select chip enable signals sound asynchrone:

Code: Select all

nCSE <= '0' when ((A(15 downto 4) = "111000000000") and (INH2 = '1') and (INH3 = '1')) else '1';
inter_nCS0 <= '0' when (INH1 = '1') and (nRD = '0') and (nMREQ = '0') and (A(15 downto 12) = "0000") else '1';
nCS0 <= inter_nCS0;
DRAM <= '1' when ((A(15 downto 12) = 0) and (INH1 = '0')) or ((A(15 downto 12) > 0) and (A(15 downto 12) < 13)) or ((A(15 downto 12) > 12) and (INH2 = '0') and (INH3 = '1')) else '0';
inter_SEL <= '1' when (sync3_nMREQ = '0') and (nMREQ = '0') and (DRAM = '1') and (nRFSH = '1') else '0';
SEL <= inter_SEL; <-- equivalent to /nCAS
nRAS <= nMREQ; <-- sounds fishy... it would be set negatively even with /CS0 = 0 or /CSE = 0. 
From Z84C0020 manual:

- Clock Cycle Time (MIN) 50ns
- Clock Edge to /MREQ Edge delay (MAX) 40ns
- Clock Edge to /RD Edge delay (MAX) 40ns
- Clock Edge to /IORQ Edge delay (MAX) 40ns

-/MREQ will fall in the first half T2 instead of the second half T1 because T1 is too short!?
-/RD will fall in the first half T2 instead of the second half T1 because T1 is too short!?
-/WR will fall in the first half Tw/T3 instead of the second half T2 because T2 is too short!?

-/IORQ will fall in the second half T2 instead of the first half T2 because T2 is too short!?
-/RD will fall in the second half T2 instead of the first half T2 because T2 is too short!?
-/WR will fall in the second half T2 instead of the first half T2 because T2 is too short!?

The fact that a half clock cycle time (25ns) may be far inferior to a max delay of 40ns is quite disturbing.

psmart
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Location: Leeds
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Re: [MZ series] Overclocking Z80

Post by psmart » Thu Aug 06, 2020 9:51 pm

Looking at the LSI you have Phi-out and Phi-in. On the MZ80A it is similar, the main crystal is divided down by the MB14298 gate array and fed into 2x74LS04's, one feeds the CPU and the other is used for timing. On the MZ-700 it looks like they are doing the same thing, feeding the clock driving the CPU, inverted Phi-out, back into the LSI as Phi-in and then probably used as the base for timing sensitive signals. If this is the case, then lifting the Phi-out pin and injecting a higher frequency should work, using the clock switch above (1 input connected to the LSI Phi-out pin, the other to the programmable second clock and the output put back to the pad where Phi-out would normally connect).

Would be good to know your outcome, as overclocking the mainboard for me is a plus, Im only overclocking the CPU at the moment. I will shortly be overclocking the MZ80A mainboard as the MB14298 gate array generates the system clocks which Im replacing with my video module, so will see what frequency I can run it at. I have a hardware MZ-700 mode now on the MZ80A which runs fine, the CPU runs at 3.58MHz, just the hardware access is at 2MHz so a bit slower compared to a real MZ-700, would be nice to overclock the hardware to 3.58MHz and have a much more accurate MZ-700 mode.

Many thanks for sharing the information.

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