HBLANK (MZ-80A)

S_U_C
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Re: HBLANK (MZ-80A)

Post by S_U_C »

I see your point.
I think the diagram 3.10 is incorrect.
Plus you can only detect 1 pluse after the Vblank
and the tempo is slow pulsing
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mz-80a
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Re: HBLANK (MZ-80A)

Post by mz-80a »

What we would like to do is wait for VLBLANK to finish, then wait for first HBLANK signal. Swap VRAM page via the memory address I/O (from $E200 onwards), wait for the next HBLANK and swap to another part of VRAM, wait for next HBLANK and swap to another part of VRAM (all these are done with simple reads of the memory mapped I/O $E200 etc) but it doesn't seem to work very well after the first couple of HBLANKs. I think we were looking to see if anyone really had any knowledge of the /WAIT states etc with regard to CPU and VRAM.
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hlide
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Re: HBLANK (MZ-80A)

Post by hlide »

Yes but sampling should be done upon $E008.D7 (BLNK pulse) and not upon $E008.D0 (TEMPO pulse) as you seem to suggest to Ben.
S_U_C
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Re: HBLANK (MZ-80A)

Post by S_U_C »

I have just had a look at the MZ80A monitor and the tempo $E008 is tested with a RRCA so it is D0, you are correct.
The miss- print is on page 163 were it states tempo D7 HBlank D0
I would still test using a mask + AND
LD A,80H
HBLK1:AND (HL) ; if (HL) = 1 ? ? ? ? ? ? ? A = 80H / if (HL) = 0 ? ? ? ? ? ? 0 A = 00H
JP NZ, HBLK1

The 20usH 40usL trace in the sevice manual is pin 8 ic 11
therefore not sure what the re-tiggerable mono-stable does to the mark space ratio.
pulse width in ns = 0.28 R C (1 +0.7/R)
R in Kohms C in pF
r=33Kohms and C =0.0022uF
and this may be the problem, if the pulse is very short some may be missed .
S_U_C
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Re: HBLANK (MZ-80A)

Post by S_U_C »

PS
There is no wait states for RAM, VRAM or ROM on the MZ80A
It is used by the EXWAIT via the bus e.g the FD card add a 1 clock pulse for FDROM access
hlide
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Re: HBLANK (MZ-80A)

Post by hlide »

20µs is indeed very short. I'm not sure why the GAL is connected to /EXWAIT as an input or as an output especially for $F000-$F3FF. It remains a mystery for me.
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Re: HBLANK (MZ-80A)

Post by hlide »

So you means when GAL decodes $F000-$F3FF, it generates one cycle /EXWAIT? That's so weird.
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Re: HBLANK (MZ-80A)

Post by hlide »

And how does MZ-80 A handle the VRAM conflict?
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Re: HBLANK (MZ-80A)

Post by mz-80a »

hlide wrote: Fri Mar 04, 2022 8:10 am And how does MZ-80 A handle the VRAM conflict?
Yes, this is a very good question!
Isn't this the reason that the MZ-80K suffers from screen snow? So how is this avoided on the 80A?
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S_U_C
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Re: HBLANK (MZ-80A)

Post by S_U_C »

I am a K pearson not a A
There is no snow on the K unless people directly poke/write data to the screen.
Printing to the screen uses the V-HBlank signal. to sycronhise the writting.
And I expect the other machines do the same.

The K as no wait signal.
If code is copied from the ROM into RAM on the K or the A there is no increase in execution time.

On the 700/800 the code will run 7% faster as the 700/800 uses a wait pulse to allow the ROM time to switch on.

If the A puts a wait pulse for F000-F3FF access it could be to allow the user to add thier own user ROM and SHARP is automatically allowing for slower EPROMS.
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